DESIGN AND EVALUATION OF AN ADAPTIVE NETWORK ON CHIP FOR MULTICORE ARCHITECTURES
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DESIGN AND EVALUATION OF AN ADAPTIVE NETWORK ON CHIP FOR MULTICORE ARCHITECTURES
Chapter one
1.1 Introduction to System on Chip
Complex applications using System On Chips (SoCs) can be created by integrating more cores, as the number of cores grows rapidly. That instance, the rapid advancement of core technology enables complicated circuits to be combined into a single chip.
This also implies that the system’s complexity grows; thus, designers seek to keep up with the rising complexity by using larger reusable blocks in their system design.
However, with these many processing units employed together to create powerful systems, linking these cores is a significant challenge. And as the number of these computing units/processing units grows and is combined onto a single silicon chip, communication between them becomes difficult.
A communication system that will support these cores needs to be created. Bus-based communication, in which bus access requests from nodes or cores are serialised through central arbiters, is a straightforward solution to the communication problem.
However, this basic solution offers various obstacles, including scalability issues, bus capacitance increases substantially as bus length and the number of cores increases, performance penalties, and wasteful power or energy as the number of cores grows.
1.2 The emergence of Network On Chip (NOC).
NoC refers to the concept of communication in System on Chips (SoCs) [6,]. This concept claims to solve the problems with bus-based communication mentioned above. Unlike bus-based communication, which uses buses and dedicated point-to-point links
Network On Chip, or NoC, employs a more general system that uses a grid of routing nodes scattered across the chip and connected by communication lines. The NoC design paradigm focuses on communication rather than computation [4].
In the on-chip network, each node (or tile) consists of a Processing Element (PE) and a communication unit known as a Network Interface (NI), as illustrated in Figure 1.
Communication between pairs of nodes is organised by connecting a network of routers and switching packages between them. Compared to typical bus-based on-chip communication designs, the NoC approach improves communication scalability, flexibility, predictability, and power economy.
Fig 1: NoC structure is consistent with related work (1.3).
Despite the fact that the notion of NoC is relatively new, it has recently received significant attention from the research community. This is due to its high potential for overcoming on-chip communication challenges.
In [6], [19], various NoC topologies are presented, with the regular mesh topology being the simplest to implement with most routing techniques.
Many routing algorithms based on wormhole routing have been developed for meshes in the literature [7], [8], [10], [15], and [16], all with the goal of enhancing the performance of routing methods Network on Chip.
These routing algorithms can be divided into three categories based on the level of adaptiveness given by the algorithms. A non-adaptive routing algorithm is deterministic, routing a packet from source to destination along a preset path.
A minimum fully adaptive routing method routes all packets via the shortest path to their destinations. A partially adaptive routing algorithm provides numerous options for routing packets via shortest paths; however, it does not allow all packets to take the shortest paths.
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